Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Create Verilog and C codes for implementing the AXI4 bus protocol on ZYNQ FPGA

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Description

Note: Take this course if you want save money in training costs of similar contents. The Official Xilinx Traning Courses cost typically from 600 USD to 4000 USD. This course is not only teaches the Zynq Processing System (PS) but also the Programmable Logic (FPGA), and the interface between them.


Published (20 Apr 2019): The GCD accelerator and UART sections will be added later, and the course price will be increased, when those sections are added.

Update 1 (22 Apr 2019): English Subtitles/CCs are enabled for this course

Update 2 (02 Jan 2020): Add bonus lecture.


What is AXI?

Advanced eXtensible Interface (AXI) is an industry-standard, system bus for the connection between CPU and peripheral in System-on-Chip (SoC) design. Today AXI version 4 (AXI4) is used in many SoC that use ARM Cortex-A processors, such as Qualcomm Snapdragon, Samsung Exynos, Broadcom (used on Raspberry Pi), and many more.

What is ZYNQ?
ZYNQ is actually a SoC, not just a FPGA, because ZYNQ consists of hard processor system (ARM Cortex-A9) and programmable logic (Xilinx 7-series FPGA, equivalent to Artix-7 FPGA). The ZYNQ device enables the implementation of custom logic such as hardware accelerator in combination with software that runs on the ARM Cortex-A9. ZYNQ can also run Linux OS, which makes this device like the popular Raspberry Pi, but with FPGA inside.


This course is based on hands-on laboratory with a lot of examples. Sample codes are provided for every project in this courses.

You will receive a certificate of completion when finishing this course. There is also Udemy 30 Day Money Back Guarantee, if you are not satisfied with this course.


So, click the course button and see you inside the course.


What You Will Learn!

  • Use Xilinx AXI4-based IP Cores
  • Create your own AXI4-based IP Cores from scratch
  • Create an AXI4-based Hardware Accelerator IP Core (GCD case study)
  • Create an AXI4-based Transceiver IP Core (UART case study)

Who Should Attend!

  • Students or engineers who are working in Embedded or SoC design
  • Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol
  • Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol