Assertions using SystemVerilog (SVA) - Foundation course
- from trenches..
Description
What is SystemVerilog Assertion (SVA)?
SVA is an integral part of IEEE-1800 SystemVerilog languages focusing on the temporal aspects of specification, modeling and verification. SVA allows sophisticated, multi-cycle assertions and functional checks to be embedded in HDL code. SVA allows simple HDL boolean expressions to be built into complex definitions of design behavior, which can be used for assertions, functional coverage, debug and formal verification.
Overview
CVC’s ABV SystemVerilog course gives you an in-depth introduction to the language, together with guidelines and methodologies to help you create, manage and debug effective assertions for complex design properties. The course is packed full of examples and case studies to demonstrate real life applications of the language.
Objectives
To explain the advantages of Assertion Based Verification (ABV) using the System Verilog Assertions (SVA).
To describe in detail the boolean, temporal, verification layers of SVA and show how the layers are used to build assertions.
To demonstrate, with examples, good and bad SVA coding styles and show workarounds for simulators with language support issues.
Prerequisites
Delegates must be able to read, write and understand VHDL or Verilog code, and be familiar with running and debugging HDL simulations. This training assumes no prior knowledge of SVA.
Table of Contents
Session 1: Introduction
Introduction to Assertions & Assertion Based Verification (ABV)
Value of assertions in Chip design flow
Session 2: ABV flow
Where does assertion fit-in design flow?
Who writes assertions?
Session 3: SVA Basics
Introduction to SystemVerilog
Assertion vs. procedural code
Types of assertions
Immediate Assertions examples
Session 4: Layers in SVA - the Pyramid structure
SVA Layers
Boolean layer
Sequence layer
Property layer
Verification directives layer
Action blocks in SVA
Session 5: SVA for Functional Coverage, constraint modeling
Using cover properties
Real life scenarios on coverage modeling
Differentiate cover vs. assert
Using assume/constraints
Session 6: Bind construct in SVA
Using external bind
Binding to instance/module
Binding to VHDL designs
Session 7: Sequences in SVA
Introduction to Temporal layer in SVA
Sequence delay operators, use models
Attempt vs thread terminology definitions
Multi-threaded sequences
Session 8: Sequence Repetition Operators
Real life scenarios on temporal behaviors
Consecutive repetition operator (seq [*])
Non-Consecutive repetition operator (signal [=])
GOTO repetition operator (seq [->])
Summary of repetition operators
Session 9: Property layer in SVA
Introduction to property..endproperty
Implication operator - overlapping (a |-> b)
Non-overlapping implication (a |=> b)
Concept of vacuity in SVA
Using disable..iff as abort condition
Session 10: System Functions in SVA
Value change functions: $rose, $fell, $stable
Vector analysis functions: $onehot/$countones etc.
Value access function: $past()
Guidelines on $rose() usage
Non-Consecutive repetition operator (
Non-Consecutive repetition operator (
What You Will Learn!
- Introduction to Assertion Based Verification (ABV)
- ABV flow
- Introduction to SystemVerilog Assertions (SVA)
- Layers in SVA
Who Should Attend!
- RTL Design Engineers
- Verification Engineers
- Design Verification leads
- VLSI DV managers